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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
(R)
Comlinear CLC1002
FEATURES n 0.6 nV/Hz input voltage noise n 1mV maximum input offset voltage n 965MHz gain bandwidth product n Minimum stable gain of 5 n 170V/s slew rate n 130mA output current n -40C to +125C operating temperature range n Fully specified at 5V and 5V supplies n CLC1002: Lead-free SOT23-6 n Future option CLC2002 APPLICATIONS n Transimpedance amplifiers n Pre-amplifier n Low noise signal processing n Medical instrumentation n Probe equipment n Test equipment n Ultrasound channel amplifier
Ultra-Low Noise Amplifier
Comlinear CLC1002 Ultra-Low Noise Amplifier
General Description
The COMLINEAR CLC1002(single) is a high-performance, voltage feedback amplifier with ultra-low input voltage noise, 0.6nV/Hz. The CLC1002 provides 965MHz gain bandwidth product and 170V/s slew rate making it well suited for high-speed data acquisition systems requiring high levels of sensitivity and signal integrity. This COMLINEAR high-performance amplifier also offers low input offset voltage. The COMLINEAR CLC1002 is designed to operate from 4V to 12V supplies. It consumes only 13mA of supply current per channel and offers a power saving disable pin that disables the amplifier and decreases the supply current to below 225A. The CLC1002 amplifier operates over the extended temperature range of -40C to +125C. If larger bandwidth or slew rate is required, a higher minimum stable gain version is available, the CLC1001 offers a minimum stable gain of 10 with 2.1GHz GBWP and 410V/s slew rate.
Typical Application - Single Supply Photodiode Amplifier
Rev 1D
Ordering Information
Part Number CLC1002IST6X CLC1002ISO8X* CLC1002ISO8* CLC1002AST6X CLC1002ASO8X* CLC1002ASO8*
*Preliminary Product Information Moisture sensitivity level for all parts is MSL-1. (c)2008 CADEKA Microcircuits LLC www.cadeka.com
Package SOT23-6 SOIC-8 SOIC-8 SOT23-6 SOIC-8 SOIC-8
Pb-Free Yes Yes Yes Yes Yes Yes
RoHS Compliant Yes Yes Yes Yes Yes Yes
Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C to +125C -40C to +125C
Packaging Method Reel Reel Rail Reel Reel Rail
Data Sheet
CLC1002 Pin Configuration
CLC1002 Pin Assignments
Pin No. Pin Name OUT -VS +IN -IN DIS +VS Description Output Negative supply Positive input Negative input Disable. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF. Positive supply 1 2 3 4 5 6
OUT -V S +IN
1 2 3 +
6
+VS DIS -IN
-
5 4
Comlinear CLC1002 Ultra-Low Noise Amplifier
SOIC Pin Configuration
SOIC Pin Assignments
Pin No. 1 Pin Name NC -IN1 +IN1 -VS NC OUT +VS DIS Description No connect Negative input Positive input Negative supply No connect Output Positive supply Disable. Enabled if pin is left floating or pulled above VON, disabled if pin is grounded or pulled below VOFF.
NC -IN1 +IN1 -V S
1 2 3 4
8 7 6 5
DIS +VS OUT NC
2 3 4 5 6 7 8
Rev 1D
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Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Comlinear CLC1002 Ultra-Low Noise Amplifier
Parameter Supply Voltage Input Voltage Range
Min 0 -Vs -0.5V
Max 14 +Vs +0.5V
Unit V V
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 6-Lead SOT23 8-Lead SOIC
Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Min -65
Typ
Max 150 150 260
Unit C C C C/W C/W
177 100
ESD Protection
Product Human Body Model (HBM) Charged Device Model (CDM) SOT23-6 2kV 2kV
Rev 1D
Recommended Operating Conditions
Parameter Operating Temperature Range (CLC1002I) Operating Temperature Range (CLC1002A) Supply Voltage Range Min -40 -40 4 Typ Max +85 +125 12 Unit C C V
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Data Sheet
Electrical Characteristics at +5V
TA = 25C, Vs = +5V, -Vs = GND, Rf = 100, RL = 500 to VS/2, G = 5; unless otherwise noted.
Symbol
GBWP BWSS BWLS BW0.1dBSS BW0.1dBLS tR, tF tS OS SR HD2 HD3 THD en in VIO dVIO Ib dIb Io PSRR AOL IS tON tOFF OFFISO OFFCOUT VOFF VON ISD RIN CIN CMIR CMRR
Parameter
-3dB Gain Bandwidth Product -3dB Bandwidth Large Signal Bandwidth 0.1dB Gain Flatness Small Signal 0.1dB Gain Flatness Large Signal Rise and Fall Time Settling Time to 0.1% Overshoot Slew Rate 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Input Voltage Noise Input Current Noise Input Offset Voltage Average Drift Input Bias Current Average Drift Input Offset Current Power Supply Rejection Ratio Open-Loop Gain Supply Current Turn On Time Turn Off Time Off Isolation Off Output Capacitance Power Down Voltage Enable Voltage Disable Supply Current Input Resistance Input Capacitance Common Mode Input Range Common Mode Rejection Ratio
Conditions
G = +21, VOUT = 0.2Vpp G = +5, VOUT = 0.2Vpp G = +5, VOUT = 2Vpp G = +5, VOUT = 0.2Vpp G = +5, VOUT = 2Vpp VOUT = 1V step; (10% to 90%) VOUT = 1V step VOUT = 1V step 4V step 1Vpp, 10MHz 1Vpp, 10MHz 1Vpp, 10MHz > 100kHz > 100kHz
Min
Typ
910 265 54 37 29 4.2 12 3 160 -72 -74 -70 0.6 4.2 0.1 2.7 28 46 0.1
Max
Units
MHz
Frequency Domain Response
Comlinear CLC1002 Ultra-Low Noise Amplifier
MHz MHz MHz MHz ns ns % V/s dBc dBc dB nV/Hz pA/Hz mV V/C A nA/C A dB dB mA ns ns dB pF V V A M pF V dB
Time Domain Response
Distortion/Noise Response
DC Performance
DC VOUT = VS / 2 per channel 1V step, 1% settling 2Vpp, 5MHz Disabled if DIS pin is grounded or pulled below VOFF Enabled if DIS pin is floating or pulled above VON No Load, DIS pin tied to ground Non-inverting
83 80 12.5 80 220 73 5.8 Disabled if DIS < 1.5 Enabled if DIS > 3 130 4.2 2 0.8 to 5.1
Rev 1D
Disable Characteristics
Input Characteristics
DC , Vcm=1.5V to 4V
94 0.97 to 4 0.96 to 4.1 125 150
Output Characteristics
VOUT IOUT ISC
Notes: 1. 100% tested at 25C (c)2007-2008 CADEKA Microcircuits LLC www.cadeka.com
Output Voltage Swing Output Current Short-Circuit Output Current
RL = 500 RL = 2k VOUT = VS / 2
V V mA mA
4
Data Sheet
Electrical Characteristics at 5V
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted.
Symbol
GBWP BWSS BWLS BW0.1dBSS BW0.1dBLS tR, tF tS OS SR HD2 HD3 THD en in VIO dVIO Ib dIb Io PSRR AOL IS tON tOFF OFFISO OFFCOUT VOFF VON ISD RIN CIN CMIR CMRR
Parameter
-3dB Gain Bandwidth Product -3dB Bandwidth Large Signal Bandwidth 0.1dB Gain Flatness Small Signal 0.1dB Gain Flatness Large Signal Rise and Fall Time Settling Time to 0.1% Overshoot Slew Rate 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Input Voltage Noise Input Current Noise Input Offset Voltage(1) Average Drift Input Bias Current (1) Average Drift Input Offset Current Power Supply Rejection Ratio Open-Loop Gain (1) Supply Current (1) Turn On Time Turn Off Time Off Isolation Off Output Capacitance Power Down Voltage Enable Voltage Disable Supply Current (1) Input Resistance Input Capacitance Common Mode Input Range Common Mode Rejection Ratio (1)
(1)
Conditions
G = +21, VOUT = 0.2Vpp G = +5, VOUT = 0.2Vpp G = +5, VOUT = 2Vpp G = +5, VOUT = 0.2Vpp G = +5, VOUT = 2Vpp VOUT = 1V step; (10% to 90%) VOUT = 1V step VOUT = 1V step 2V step 2Vpp, 10MHz 2Vpp, 10MHz 2Vpp, 5MHz > 100kHz > 100kHz
Min
Typ
965 290 61 45 32 3.8 12 2 170 -75 -66 -65.5 0.6 4.2
Max
Units
MHz
Frequency Domain Response
Comlinear CLC1002 Ultra-Low Noise Amplifier
MHz MHz MHz MHz ns ns % V/s dBc dBc dB nV/Hz pA/Hz 1 60 6 mV V/C A nA/C A dB dB 16 mA ns ns dB pF V V 225 A M pF V dB 3.6 V V mA mA
Time Domain Response
Distortion/Noise Response
DC Performance
-1 -60 0.5 4.3 30 44 0.3 DC VOUT = VS / 2 per channel 1V step, 1% settling 2Vpp, 5MHz Disabled if DIS pin is grounded or pulled below VOFF Enabled if DIS pin is floating or pulled above VON No Load, DIS pin tied to ground Non-inverting 78 70 83 83 13 115 210 73 5.7 Disabled if DIS < 1.3 Enabled if DIS > 3 180 9.4 1.82 -4.3 to 5 DC , Vcm=-3.5V to 4V RL = 500 (1) RL = 2k VOUT = VS / 2 75 -3.3 90 4 4 130 165
Rev 1D
Disable Characteristics
Input Characteristics
Output Characteristics
VOUT IOUT ISC
Notes: 1. 100% tested at 25C
Output Voltage Swing Output Current Short-Circuit Output Current
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Data Sheet
Typical Performance Characteristics
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. Non-Inverting Frequency Response
3
Inverting Frequency Response
Comlinear CLC1002 Ultra-Low Noise Amplifier
3
Normalized Gain (dB)
0 G = +5 -3 G = +10 G = +20 -6 VOUT = 0.2Vpp -9 0.1 1 10 100 1000
Normalized Gain (dB)
0 G = -5 -3 G = -10 G = -20 -6 VOUT = 0.2Vpp -9 0.1 1 10 100 1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL
3 CL = 470pF Rs = 4.3
Frequency Response vs. RL
3
Normalized Gain (dB)
Normalized Gain (dB)
0 CL = 100pF Rs = 12 -3 CL = 47pF Rs = 20 CL = 22pF Rs = 30 VOUT = 0.2Vpp -9 0.1 1 10 100 1000 CL = 10pF Rs = 43
0
Rl = 1K Rl = 2K Rl = 5K
-3
Rev 1D
-6
VOUT = 0.2Vpp -6 0.1 1 10 100 1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT
1 0
-3dB Bandwidth vs. Output Voltage
350 300
-3dB Bandwidth (MHz)
100 1000
Normalized Gain (dB)
-1 -2 -3 -4 -5 -6 -7 0.1 1
VOUT = 4Vpp VOUT = 3Vpp VOUT = 2Vpp
250 200 150 100 50 0
10
0.0
1.0
2.0
3.0
4.0
Frequency (MHz)
VOUT (VPP)
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Data Sheet
Typical Performance Characteristics
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. Non-Inverting Frequency Response at VS = 5V
3
Inverting Frequency Response at VS = 5V
Comlinear CLC1002 Ultra-Low Noise Amplifier
3
Normalized Gain (dB)
0 G = +5 -3 G = +10 G = +20 -6 VOUT = 0.2Vpp -9 0.1 1 10 100 1000
Normalized Gain (dB)
0 G = -5 -3 G = -10 G = -20 -6 VOUT = 0.2Vpp -9 0.1 1 10 100 1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL at VS = 5V
3 CL = 470pF Rs = 4.3
Frequency Response vs. RL at VS = 5V
3
Normalized Gain (dB)
Normalized Gain (dB)
0 CL = 100pF Rs = 13 -3 CL = 47pF Rs = 20 CL = 22pF Rs = 33 VOUT = 0.2Vpp -9 0.1 1 10 100 1000 CL = 10pF Rs = 50
0
Rl = 1K Rl = 2K Rl = 5K
-3
Rev 1D
-6
VOUT = 0.2Vpp -6 0.1 1 10 100 1000
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT at VS = 5V
1 0
-3dB Bandwidth vs. Output Voltage at VS = 5V
350 300
-3dB Bandwidth (MHz)
100 1000
Normalized Gain (dB)
-1 -2 -3 -4 -5 -6 -7 0.1 1
VOUT = 2Vpp VOUT = 1.5Vpp VOUT = 1Vpp
250 200 150 100 50 0
10
0.0
0.5
1.0
1.5
2.0
Frequency (MHz)
VOUT (VPP)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. Input Voltage Noise
2.8 2.6 2.4
Input Voltage Noise at VS = 5V
2.8 2.6 2.4
Comlinear CLC1002 Ultra-Low Noise Amplifier
Input Voltage Noise (nV/Hz)
2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.0001 0.001 0.01 0.1 1 10
Input Voltage Noise (nV/Hz)
2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0.0001 0.001 0.01 0.1 1 10
Frequency (MHz)
Frequency (MHz)
Input Voltage Noise (>10kHz)
0.9 0.85
Input Voltage Noise at VS = 5V (>10kHz)
0.9 0.85
Input Voltage Noise (nV/Hz)
0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.01 0.1 1 10 10
Input Voltage Noise (nV/Hz)
0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.01 0.1 1 10 10
Rev 1D
Frequency (MHz)
Frequency (MHz)
ROUT vs. Frequency
10
ROUT ()
1
0.1
0.01 0.001 0.01 0.1 1 10 100
Frequency (MHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. 2nd Harmonic Distortion vs. RL
-55
3rd Harmonic Distortion vs. RL
-55
Comlinear CLC1002 Ultra-Low Noise Amplifier
-65
RL = 500
-65
RL = 500
Distortion (dBc)
-75
Distortion (dBc)
-75
-85
RL = 1k
-85
RL = 1k
-95 VOUT = 1Vpp -105 5 10 15 20
-95 VOUT = 1Vpp -105 5 10 15 20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT
-45 -50 -55 -60 20MHz
3rd Harmonic Distortion vs. VOUT
-45 -50 -55 -60 20MHz
Distortion (dBc)
-65 -70 -75 -80 -85 -90 -95 -100 10MHz 5MHz RL = 500 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Distortion (dBc)
-65 -70 -75 -80 -85 -90 -95 -100 10MHz RL = 500 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 5MHz
Rev 1D
Output Amplitude (Vpp)
Output Amplitude (Vpp)
2nd Harmonic Distortion vs. Gain
-50 -55 -60 AV+20
3rd Harmonic Distortion vs. Gain
-50 -55 -60 AV+20
Distortion (dBc)
-65 -70 -75 -80 -85 -90 5 10 Frequency (MHz) 15 20 AV+10 VOUT = 1Vpp RL = 500 AV+5
Distortion (dBc)
-65 -70 -75 -80 -85 -90 5 VOUT = 1Vpp RL = 500 10 Frequency (MHz) 15 20 AV+10 AV+5
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. 2nd Harmonic Distortion vs. RL at VS = 5V
-55
3rd Harmonic Distortion vs. RL at VS = 5V
-55
Comlinear CLC1002 Ultra-Low Noise Amplifier
-65
RL = 500
-65
RL = 500
Distortion (dBc)
-75 RL = 1k
Distortion (dBc)
-75
-85
-85
RL = 1k
-95 VOUT = 1Vpp -105 5 10 15 20
-95 VOUT = 1Vpp -105 5 10 15 20
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT at VS = 5V
-45 -50 -55 -60 20MHz
3rd Harmonic Distortion vs. VOUT at VS = 5V
-45 -50 -55 -60 20MHz
Distortion (dBc)
-65 -70 -75 -80 -85 -90 -95 -100 RL = 500 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 10MHz 5MHz
Distortion (dBc)
-65 -70 -75 -80 -85 -90 -95 -100 10MHz RL = 500 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 5MHz
Rev 1D
Output Amplitude (Vpp)
Output Amplitude (Vpp)
2nd Harmonic Distortion vs. Gain at VS = 5V
-50 -55 -60 AV+20
3rd Harmonic Distortion vs. Gain Freq at VS = 5V
-50 -55 -60 AV+20
Distortion (dBc)
-65 -70 -75 -80 -85 -90 5 VOUT = 1Vpp RL = 500
Distortion (dBc)
AV+10
-65 -70 -75 -80 -85 -90 VOUT = 1Vpp RL = 500 5 10 Frequency (MHz) 15 20 AV+10 AV+5
AV+5
10 Frequency (MHz)
15
20
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. Small Signal Pulse Response
0.15 0.1 0.05
Small Signal Pulse Response at VS = 5V
2.65 2.6 2.55
Comlinear CLC1002 Ultra-Low Noise Amplifier
Voltage (V)
0 -0.05 -0.1 -0.15 0 50 100 150 200
Voltage (V)
2.5 2.45 2.4 2.35 0 50 100 150 200
Time (ns)
Time (ns)
Large Signal Pulse Response
3 2 1
Large Signal Pulse Response at VS = 5V
4 3.5 3
Voltage (V)
0 -1 -2 -3 0 50 100 150 200
Voltage (V)
2.5 2 1.5 1 0 50 100 150 200
Rev 1D
Time (ns)
Time (ns)
Enable Response
5.5 4.5 Enable 1 1.5
Disable Response
5.5 Disable 4.5 1 1.5
Disable Voltage (V)
Output Voltage (V)
Output Voltage (V)
Enable Voltage (V)
3.5 2.5 1.5 0 0.5 -0.5 -50 0 50 100 150 200 -0.5 0.5
3.5 Output 2.5 1.5 0 0.5 -0.5 -100 0 100 200 300 400 -0.5 0.5
Output
Time (ns)
Time (ns)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 100, RL = 500 , G = 5; unless otherwise noted. Enable Response at VS = 5V
5.5 4.5 Enable 1 1.5
Disable Response at VS = 5V
5.5 Disable 4.5 1 1.5
Comlinear CLC1002 Ultra-Low Noise Amplifier
Disable Voltage (V)
Output Voltage (V)
Output Voltage (V)
Enable Voltage (V)
3.5 2.5 1.5 0 0.5 -0.5 -50 0 50 100 150 200 -0.5 0.5
3.5 2.5 1.5 0 0.5 -0.5 -100 0 100 200 300 400 -0.5 Output 0.5
Output
Time (ns)
Time (ns)
Off Isolation
-40 -45 -50 -55
Off Isolation at VS = 5V
-40 -45 -50 -55
Off Isolation (dB)
-60 -65 -70 -75 -80 -85 -90 -95 1 10 100 VOUT = 2Vpp
Off Isolation (dB)
-60 -65 -70 -75 -80 -85 -90 -95 1 10 100 VOUT = 2Vpp
Rev 1D
Frequency (MHz)
Frequency (MHz)
CMRR vs. Frequency
100
PSRR vs. Frequency
100
80
80
CMRR (dB)
40
PSRR (dB)
0.01 0.1 1 10 100
60
60
40
20
20
0 0.001
0 0.001 0.01 0.1 1 10 100
Frequency (MHz)
Frequency (MHz)
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Data Sheet
Application Information
Basic Operation Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
+Vs 6.8F
versus Rf and Rg. As the value of Rf increases, the total input referred noise also increases.
3 2.75
Input Referred Noise (nV/rtHz)
2.5 2.25 2 1.75 1.5 1.25 1 0.75 G = +21 G = +11
G = +5
Comlinear CLC1002 Ultra-Low Noise Amplifier
Input
+ -
0.1F Output 0.1F RL Rf
G = 1 + (Rf/Rg)
0.5 100 1000
Rf (Ohms)
Figure 3: Input Referred Voltage Noise vs. Rf and Rg
Rg -Vs
6.8F
The noise caused by a resistor is modeled with either a voltage source in series with the resistance: 4kTR
Figure 1. Typical Non-Inverting Gain Circuit
+Vs 6.8F
Or a current source in parallel with it:
R1 Input Rg + 0.1F 6.8F -Vs Rf
G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg
0.1F Output RL
iR =
4kT R
Rev 1D
Op amp noise is modeled with three noise sources, en, in and ii. These three sources are analogous to the DC input voltage and current errors Vos, Ibn and Ibi.
Figure 2. Typical Inverting Gain Circuit The noise models must be analyzed in-circuit to determine the effect on the op amp output noise. Achieving Low Noise in an Application Making full use of the low noise of the CLC1002 requires careful consideration of resistor values. The feedback and gain set resistors (Rf and Rg) and the non-inverting source impedance (Rsource) all contribute noise to the circuit and can easily dominate the overall noise if their values are too high. The datasheet is specified with an Rg of 25, at which point the noise from Rf and Rg is about equal to the noise from the CLC1002. Lower value resistors could be used at the expense of more distortion. Figure 3 shows total input voltage noise (amp+resistors) Since noise is statistical in nature rather than a continuous signal, the set of noise sources in circuit add in an RMS (root mean square) fashion rather than in a linear fashion. For uncorrelated noise sources, this means you add the squares of the noise voltages. A typical non-inverting application (see figure 1) results in the following noise at the output of the op amp:
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13
Data Sheet
2 e2 = en o
1+
Rg
Rf
2
+ in2Rs 2 1+
Rg
Rf
2
Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include + ii2R2 op amp noise terms en , in and ii f the effect of the feedback network. For instance, Rloadeff in figure 3 would be calculated as: RL || (Rf + Rg)
op amp noise terms en, in and ii
Comlinear CLC1002 Ultra-Low Noise Amplifier
These measurements are basic and are relatively easy to + external resistor noiseperform with standard Rf equipment. For design purposes terms for Rs, Rg and lab + 1+ + Rg Rg however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. external resistor noise terms for RS, Rg and Rf Here, PD can be found from
2 eRs
Rf
2
e2 Rg
Rf
2
e2 Rf
High source impedances are sometimes unavoidable, but they increase noise from the source impedance and also make the circuit more sensitive to the op amp current noise. Analyze all noise sources in the circuit, not just the op amp itself, to achieve low noise in your application.
PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff
Power Dissipation Power dissipation should not be a factor when operating under the stated 500 load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. TJunction = TAmbient + (JA x PD) Where TAmbient is the temperature of the working environment. In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply x IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is:
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The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available.
2.5
Rev 1D
Maximum Power Dissipation (W)
2
SOIC-8
1.5
SOT23-6
1
0.5
0 -40 -20 0 20 40 60 80 100 120
Ambient Temperature (C)
Figure 4. Maximum Power Derating
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Data Sheet
Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 5.
Input + Rf Rg Rs CL RL
3 G=5 2 1 0 Input -1 -2 -3 0 50 100 150 200 250 300 350 400 450 Output
6 4
Output Voltage (V)
Input Voltage (V)
2 0 -2 -4 -6
Comlinear CLC1002 Ultra-Low Noise Amplifier
Output
Time (us)
Figure 5. Addition of RS for Driving Capacitive Loads Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB peaking in the frequency response. The Frequency Response vs. CL plots, on page 7, illustrates the response of the CLC1002.
CL (pF) 10 22 47 100 470 RS () 43 30 20 12 4.3 -3dB BW (MHz) 275 235 190 146 72
Figure 6. Overdrive Recovery Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CaDeKa has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information.
Rev 1D
Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC1002 will typically recover in less than 25ns from an overdrive condition. Figure 6 shows the CLC1002 in an overdriven condition.
Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # CEB002 CEB003 Products CLC1002 in SOT23-5 CLC1002 in SOIC-8
(c)2007-2008 CADEKA Microcircuits LLC
www.cadeka.com
15
Data Sheet
Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 7-11. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane.
Comlinear CLC1002 Ultra-Low Noise Amplifier
Figure 9. CEB002 Bottom View
Rev 1D
Figure 7. CEB002/CEB003 Schematic
Figure 10. CEB003 Top View
Figure 8. CEB002 Top View
(c)2007-2008 CADEKA Microcircuits LLC
Figure 11. CEB003 Bottom View
www.cadeka.com
16
Data Sheet
Mechanical Dimensions
SOT23-6 Package
Comlinear CLC1002 Ultra-Low Noise Amplifier
SOIC-8 Package
Rev 1D
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2007-2008 by CADEKA Microcircuits LLC. All rights reserved.
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